Search found 9 matches

by jfollas
Wed Feb 08, 2017 8:17 am
Forum: Report Bugs
Topic: Additional beacon being sent after last CSA beacon
Replies: 2
Views: 1517

Re: Additional beacon being sent after last CSA beacon

Possible related bug (maybe it's a feature request?): wifi_set_channel() does not have any impact when the SoftAP is running (i.e., when the Station is disconnected). My hope would be to use wifi_set_channel() to cause a Channel Switch Announcement to be issued so that all of the connected STAs woul...
by jfollas
Tue Feb 07, 2017 9:24 am
Forum: Report Bugs
Topic: Additional beacon being sent after last CSA beacon
Replies: 2
Views: 1517

Additional beacon being sent after last CSA beacon

I recently discovered that the ESP8266 (SDK 2.0.0) broadcasts Channel Switch Announcements (defined in 802.11h) when the STA connects while in STATIONAP mode and the STA channel is different than the already-running SoftAP channel. However, looking at Wireshark logs, I see that there's an additional...
by jfollas
Tue Jun 07, 2016 1:03 am
Forum: Documentation Request
Topic: When is SPI MISO sampled?
Replies: 5
Views: 5660

Re: When is SPI MISO sampled?

For the purpose of this post, I was referring to using the ESP as a master. In a recent enhancement to the NodeMCU firmware, we added support for Mode 2 and Mode 3. The MOSI edge (master out, or when the ESP sets the bit from the master) is successfully set using the SPI_CK_OUT_EDGE. However, the MI...
by jfollas
Sun Mar 20, 2016 11:02 am
Forum: Documentation Request
Topic: When is SPI MISO sampled?
Replies: 5
Views: 5660

When is SPI MISO sampled?

SPI bits are supposed to be set on one clock edge and then read on the next. https://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus#Clock_polarity_and_phase For example: Mode 0 (CPOL=0, CPHA=0) sets the bit on the falling edge, and then samples on the next rising edge. Mode 1 (CPOL=0, CPHA=1)...
by jfollas
Fri Jan 15, 2016 4:09 am
Forum: ESP8266 HDK
Topic: (H)SPI configuration options
Replies: 7
Views: 5431

Re: (H)SPI configuration options

I think you're looking to do this to use mode 2 or 3:

Code: Select all

if (cpol == 1) {
    SET_PERI_REG_MASK(SPI_PIN(spi_no), SPI_IDLE_EDGE);
} else {
    CLEAR_PERI_REG_MASK(SPI_PIN(spi_no), SPI_IDLE_EDGE);
}


It's not SPI_CTRL2 that controls the clock polarity, but SPI_PIN bit 29.
by jfollas
Thu Jan 14, 2016 10:46 am
Forum: Documentation Request
Topic: HSPI CPOL
Replies: 2
Views: 2441

Re: HSPI CPOL

Initial tests with the logic analyzer looks perfect for setting the SPI_IDLE_EDGE bit on SPI_PIN to enable CPOL=1. Thanks so much! I know this has been a HUGE mystery for a long time now.
by jfollas
Fri Jan 01, 2016 12:42 pm
Forum: Documentation Request
Topic: HSPI CPOL
Replies: 2
Views: 2441

HSPI CPOL

Need documentation explaining how to set the HSPI clock polarity to CPOL=1. CPOL=1 will result in a SPI clock signal like this (it will be high when idle): ____________ _ _ _ _ _ _ _ ____________ |_| |_| |_| |_| |_| |_| |_| |_| Some people suggest that it is a setting of SPI_CTRL2. What are bits 15:...
by jfollas
Fri Jan 01, 2016 12:34 pm
Forum: ESP8266 HDK
Topic: Is there a serial number or unique ID in the chip
Replies: 7
Views: 14080

Re: Is there a serial number or unique ID in the chip

Dear Sir, CHIP_ID can not be used to uniquely indicate of ESP8266EX, because the chip_id of chips for the same batch is same. You can use MAC address as the identifier. MAC address is pre-burned in the chip by efuse before delivery and MAC address of each chip are different. This does not sound rig...
by jfollas
Sun Oct 18, 2015 1:46 pm
Forum: ESP8266 HDK
Topic: (H)SPI configuration options
Replies: 7
Views: 5431

Re: (H)SPI configuration options

This seems to be an ongoing bug, short of any documentation to show how polarity can be achieved. Polarity does not refer to when during the clock cycle that MOSI and MISO signals are sampled for new bits. That's the Phase, and we seem to be able to control that on the USER register. Polarity is the...

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