Hi there!
Experimenting with overlapping SPI funcionality... giving the sensitivity/difficulties in debugging such setup (because of the running code accessing the primary SPI flash) I would ask for some clarifications.
So, the ESP has two SPI units, so called SPI (primary, where the flash is usually attached) and the HSPI (secondary, free for user). Each SPI module is using its set of SPI registers (#define REG_SPI_BASE(i) (0x60000200 - i*0x100)).
Which pins/functions are used for 2 and 4 bit SPI mode operation? I suppose the one labelled SPIxxx and HSPIxxx, right? If that's right the HSPI module cannot work in 2 or 4 bit mode because some pins overlap with the primary SPI module:
Is that right?
MTDI_U.......... MTDI.........I2SI_DATA.....HSPIQ....GPIO12
MTCK_U..........MTCK........I2SI_BCK.......HSPID....GPIO13
MTMS_U..........MTMS........I2SI_WS........HSPICLK...GPIO14
MTDO_U..........MTDO.......I2SO_BCK ......HSPICS....GPIO15
U0RXD_U.........U0RXD......I2SO_DATA.....GPIO3......CLK_XTAL
U0TXD_U.........U0TXD......SPICS1..........GPIO1......CLK_RTC
SD_CLK_U........SD_CLK.....SPICLK.........GPIO6.....U1CTS
SD_DATA0_U....SD_DATA0...SPIQ...........GPIO7.....U1TXD
SD_DATA1_U....SD_DATA1...SPID...........GPIO8.....U1RXD
SD_DATA2_U....SD_DATA2...SPIHD.........GPIO9.....HSPIHD
SD_DATA3_U....SD_DATA3...SPIWP.........GPIO10.....HSPIWP
SD_CMD_U ......SD_CMD......SPICS0.........GPIO11.....U1RTS
GPIO0_U........GPIO0 ........SPICS2.........CLK_OUT
GPIO2_U........GPIO2 ........I2SO_WS.......U1TXD.....U0TXD
I suppose the xSPIHD and xSPIWP pins/functions are the pins/bits 2 and 3 for 4-bit SPI mode? Or the 4-bit mode uses the SD_xxx functions/pins?
Can the HSPI module use 4-bit transfer when configured for SPI Overlap? (using the same pins as primary?)
The running code fetching is done using the SPI module, right? Changing the SPI registers will affect the code execution/fetching, right? And probably cause the chip resetting or hanging?
If using overlapping mode, how many bytes can be read/written in one "block" - 64 bytes/512 bits? As the buffer is 64 bytes (if using all for write or read) and the number of bits in REG_USR_xx_BITLEN is 9 bits?
How long/big are the chunks of data (well, code) handled by the primary SPI module for code execution? Does the CPU always read/write 64 bytes a time when accessing the SPI flash?
When SPI modules work in Overlap mode and a transfer is started, will it send the entire buffer in one "piece" or the transfer can be interrupted by the primary SPI module?
For example, if I put 24 bytes in SPI buffer and issue a 192 bit data transfer (REG_USR_MISO_BITLEN=191) are all the 24 bytes transferred without interruption (from the primary SPI module)?
How are the SPI modules sharing the pins? Equal priority or no?
For example, if I want to send 100KB of data though HSPI using 512 bit transfers, loading the hspi buffer on transfer complete interrupt and at the same time read some data from SPI flash with spi_flash_read(src, buf, )... how will the transfer look?
Pseudo code:
Code: Select all
volatile char buffer[256];
hspi_transfer_end_ISR:
memcpy(buffer, hspi_buffer) // fill hspi_buffer with new 64 bytes of data
start new hspi transfer (512 bits) // send out the hspi buffer
end interrupt
main:
start hspi transfer (SPI_CMD(SPI_USR)=1)
repeat
spi_flash_read(src, buffer, 256)
do_calculations
src=src+256
until src < 10000
will the SPI access look like this:
HSPI: write 512 bits
SPI: read 512 bits
HSPI: write 512 bits
SPI: read 512 bits
HSPI: write 512 bits
etc
or more like this:
HSPI: write 512 bits
SPI: read 512 bits // spi_flash_read() is blocking, right
SPI: read 512 bits
SPI: read 512 bits
SPI: read 512 bits
HSPI: write 512 bits
SPI: read 512 bits // spi_flash_read() is blocking, right
SPI: read 512 bits
SPI: read 512 bits
SPI: read 512 bits
etc.
Also, how will the code execution (loading code from flash to IRAM) affect such "interrupt driven large/bulk" transfers on HSPI module?
Thanks for any info.
Regards,
