HSPI CPOL

jfollas
Posts: 9
Joined: Sun Oct 18, 2015 1:23 pm

HSPI CPOL

Postby jfollas » Fri Jan 01, 2016 12:42 pm

Need documentation explaining how to set the HSPI clock polarity to CPOL=1.

CPOL=1 will result in a SPI clock signal like this (it will be high when idle):

Code: Select all

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Some people suggest that it is a setting of SPI_CTRL2. What are bits 15:0 of SPI_CTRL2 used for?

ESP_Sprite
Posts: 25
Joined: Fri Oct 24, 2014 7:58 pm

Re: HSPI CPOL

Postby ESP_Sprite » Tue Jan 05, 2016 11:28 am

Seems the bit for that went undocumented in the SDK code. In the SPI_PIN register, can you try setting bit 29? This should do what you want. We will include a definition for it in the next SDK, for now you can use this one:
#define SPI_IDLE_EDGE (BIT(29))

jfollas
Posts: 9
Joined: Sun Oct 18, 2015 1:23 pm

Re: HSPI CPOL

Postby jfollas » Thu Jan 14, 2016 10:46 am

Initial tests with the logic analyzer looks perfect for setting the SPI_IDLE_EDGE bit on SPI_PIN to enable CPOL=1. Thanks so much! I know this has been a HUGE mystery for a long time now.

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