In the I2SCONF register bits 12-15 signify the number of extra bits shifted out after each 16 bits. Using 4 bits however, I cannot set this to 16, which would be required for 24-bit audio data within a 32-bit sample. The Rx FIFO mode in bits 16-18 of the I2S_FIFO_CONF register is set to 2 (= 24 bits per channel full data discontinue). Looking at the data being received from the ADC, it seems that the most significant bit is lost when I set I2S_BITS_MOD to 15.
How do I setup the I2S registers to receive 24-bit audio data in a 32-bit word?
Which register map file are you referring to when programming the I2S registers? Can you please attach that?
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