XPD_DCDC state while in deep sleep

hatus
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Joined: Sat Nov 05, 2016 1:27 pm
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XPD_DCDC state while in deep sleep

Postby hatus » Wed May 17, 2017 12:33 pm

Hi,

I'd like to know what is the XPD_DCDC state while the ESP8285 is in deep sleep.

Is it at high logic level?

Or is it at high impedance?

In other words: Is it an open drain GPIO during deep sleep?

Thank you.

Best regards,
Hatus

ESP_Faye
Posts: 1592
Joined: Mon Oct 27, 2014 11:08 am

Re: XPD_DCDC state while in deep sleep

Postby ESP_Faye » Thu May 18, 2017 2:33 pm

Hi,

You can refer to the ESP8266 Pin List: http://www.espressif.com/en/support/download/documents.
It is at high logic level.

Thanks for your interest in ESP8266 !

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