ESP8266 Developer Zone

Re: HSPI PORT OVERLAP MODE DEMO

2016-08-02T14:35:24+08:00

hi,

i want to connect two esp using SPI for freeRTOS SDK.
i got some libs but i don't find any function for make esp device as a slave.
so, can anyone guide me how can i make any esp device as a spi slave device in freeRTOS.

regards,
Valmik Thakar

Statistics: Posted by valmik thakar — Tue Aug 02, 2016 2:35 pm

Re: HSPI PORT OVERLAP MODE DEMO

2016-04-20T18:30:09+08:00

Hello, I found this post over Google. I have question. It is possible connect to display any other SPI device (for example SRAM)? Or otherwise. It is possible connect to SPI to which it is attached FLASH two SPI device? If yes, how to setup CS for two device? Thank you a lot.

MG

Statistics: Posted by mgrunt — Wed Apr 20, 2016 6:30 pm

Re: HSPI PORT OVERLAP MODE DEMO

2015-11-28T13:14:56+08:00

Hi,

I am newbie for ESP-WROOM-02 Module and started to work on it. I have flashed and started AT firmware successfully without any issue. I have also executed some AT commands on that module which works fine without any issue.

Now, I have one OLED LCD and I want to connect it over SPI Interface. I know that there are HSPI Lines which are shared with GPIOs and UART Pins in this ESP-WROOM-02 Module.

Does you demo esp_iot_sdk_v0.9.2_hspi_overlap will work for ESP-WROOM-02 Wifi Module with OLED LCD connected over HSPI Lines?

Do I need to change any configurations or code to work your demo with ESP-WROOM-02 Module?

Please provide me Hardware Connection Details to connect OLED LCD with ESP-WROOM-02 WIfi Module.

Regards,
Ritesh Prajapati

Statistics: Posted by ritesh — Sat Nov 28, 2015 1:14 pm

Re: HSPI PORT OVERLAP MODE DEMO

2015-03-25T12:32:01+08:00

First of all thanks for the fast response!

I'm aware of the stuff you just wrote.

I was wondering if you know what will happen when a large/long read/write is done simultaneously on both SPI and HSPI?

For example, I want to send 100K of data over the HSPI port (in overlap mode, using interrupts on transfer complete) and other code continues to execute so actually the primary SPI is also used for fetching code to ICACHE.
Will the SPI/HSPI "sharing" happens equally (one packet/transfer for SPI one for HSPI) or will the HW switch to SPI until all required is read and only then switch back to HSPI? (priority?)

Also, is it possible to configure two (or more) SPI flashes on the SPI bus? The HW has CS0, CS1... but how to tell the CPU at which address is mapped the flash? So it could select the appropriate CS line?
Is this possible?

Statistics: Posted by mculibrk — Wed Mar 25, 2015 12:32 pm

Re: HSPI PORT OVERLAP MODE DEMO

2015-03-25T12:21:21+08:00

This overlap mode will swap the HSPI port to the main SPI port.
//hspi overlap to spi, two spi masters on cspi
SET_PERI_REG_MASK(HOST_INF_SEL, reg_cspi_overlap);
So if we control the HSPI lines it acts on the main SPI lines.

There is a hardware arbiter to decide which line(CS0/CS1/CS2) should be selected.

So we need to set the CS line for HSPI and SPI,
//select HSPI CS2 ,disable HSPI CS0 and CS1
CLEAR_PERI_REG_MASK(SPI_PIN(HSPI), SPI_CS2_DIS);
SET_PERI_REG_MASK(SPI_PIN(HSPI), SPI_CS0_DIS |SPI_CS1_DIS);

As well as to set the priority of HSPI and SPI, so that the flash ICACHE reading would be execute firstly by switching the CS line.
//set higher priority for spi than hspi,
SET_PERI_REG_MASK(SPI_EXT3(SPI),0x1);
SET_PERI_REG_MASK(SPI_EXT3(HSPI),0x3);
SET_PERI_REG_MASK(SPI_USER(HSPI), BIT(5));

So , in this mode , we write the LCD on HSPI port , it disable the main SPI CS , enable the HSPI CS line, since we swap the port already , it reflects on the SPI port.
But the FLASH would not be burned because of the automatic CS selection.
Meanwhile , we already set the SPI prior to the HSPI , so if there is a command on SPI, the hardware would switch to the SPI CS line, then, back to HSPI CS after it's done.

Statistics: Posted by costaud — Wed Mar 25, 2015 12:21 pm

Re: HSPI PORT OVERLAP MODE DEMO

2015-03-22T11:23:56+08:00

Hi there!

Experimenting with overlapping SPI funcionality... giving the sensitivity/difficulties in debugging such setup (because of the running code accessing the primary SPI flash) I would ask for some clarifications.

So, the ESP has two SPI units, so called SPI (primary, where the flash is usually attached) and the HSPI (secondary, free for user). Each SPI module is using its set of SPI registers (#define REG_SPI_BASE(i) (0x60000200 - i*0x100)).

Which pins/functions are used for 2 and 4 bit SPI mode operation? I suppose the one labelled SPIxxx and HSPIxxx, right? If that's right the HSPI module cannot work in 2 or 4 bit mode because some pins overlap with the primary SPI module:
Is that right?

HSPIQ

HSPID

HSPICLK

HSPICS

SPICLK

SPIQ

SPID

SPIHD

HSPIHD

SPIWP

HSPIWP

I suppose the xSPIHD and xSPIWP pins/functions are the pins/bits 2 and 3 for 4-bit SPI mode? Or the 4-bit mode uses the SD_xxx functions/pins?

Can the HSPI module use 4-bit transfer when configured for SPI Overlap? (using the same pins as primary?)

The running code fetching is done using the SPI module, right? Changing the SPI registers will affect the code execution/fetching, right? And probably cause the chip resetting or hanging?

If using overlapping mode, how many bytes can be read/written in one "block" - 64 bytes/512 bits? As the buffer is 64 bytes (if using all for write or read) and the number of bits in REG_USR_xx_BITLEN is 9 bits?
How long/big are the chunks of data (well, code) handled by the primary SPI module for code execution? Does the CPU always read/write 64 bytes a time when accessing the SPI flash?
When SPI modules work in Overlap mode and a transfer is started, will it send the entire buffer in one "piece" or the transfer can be interrupted by the primary SPI module?
For example, if I put 24 bytes in SPI buffer and issue a 192 bit data transfer (REG_USR_MISO_BITLEN=191) are all the 24 bytes transferred without interruption (from the primary SPI module)?

How are the SPI modules sharing the pins? Equal priority or no?
For example, if I want to send 100KB of data though HSPI using 512 bit transfers, loading the hspi buffer on transfer complete interrupt and at the same time read some data from SPI flash with spi_flash_read(src, buf, )... how will the transfer look?
Pseudo code:

Code:


volatile char buffer[256];

hspi_transfer_end_ISR:
  memcpy(buffer, hspi_buffer)                   // fill hspi_buffer with new 64 bytes of data
  start new hspi transfer (512 bits)             // send out the hspi buffer
  end interrupt

main:
  start hspi transfer (SPI_CMD(SPI_USR)=1)

  repeat
      spi_flash_read(src, buffer, 256)
      do_calculations
      src=src+256
  until src < 10000

will the SPI access look like this:
HSPI: write 512 bits
SPI: read 512 bits
HSPI: write 512 bits
SPI: read 512 bits
HSPI: write 512 bits
etc

or more like this:
HSPI: write 512 bits
SPI: read 512 bits // spi_flash_read() is blocking, right
SPI: read 512 bits
SPI: read 512 bits
SPI: read 512 bits
HSPI: write 512 bits
SPI: read 512 bits // spi_flash_read() is blocking, right
SPI: read 512 bits
SPI: read 512 bits
SPI: read 512 bits
etc.

Also, how will the code execution (loading code from flash to IRAM) affect such "interrupt driven large/bulk" transfers on HSPI module?

Thanks for any info.

Regards,

Statistics: Posted by mculibrk — Sun Mar 22, 2015 11:23 am

Re: HSPI PORT OVERLAP MODE DEMO

2015-02-15T12:01:41+08:00

vitogeng wrote:
Hi!
you demo is great, but I have a question, how is it reading data from spi?

The hardware will toggle the CS line automatically.

Statistics: Posted by costaud — Sun Feb 15, 2015 12:01 pm

Re: HSPI PORT OVERLAP MODE DEMO

2014-12-10T16:16:08+08:00

Hi!
you demo is great, but I have a question, how is it reading data from spi?

Statistics: Posted by vitogeng — Wed Dec 10, 2014 4:16 pm

Re: HSPI PORT OVERLAP MODE DEMO

2014-11-24T06:03:28+08:00

perfect!
txs costaud for sharing! will follow your's.
best wishes
rudi

Statistics: Posted by rudi — Mon Nov 24, 2014 6:03 am

HSPI PORT OVERLAP MODE DEMO

2014-11-24T02:06:03+08:00

This overlap mode means that the hspi module can be re-mapping to the spi port.

After setting the higher priority to the spi port than to the hspi port , the hardware arbiter will switch these two port automatically via controlling the separate CS pins.

In this mode , the two spi modules share the same pins, so that the hspi pin mux can be configured as gpios or other functions.

The key point is the overlap mode config:

Code:

void ICACHE_FLASH_ATTR
    hapi_overlap_init()
{
   //hspi overlap to spi, two spi masters on cspi
   SET_PERI_REG_MASK(HOST_INF_SEL, reg_cspi_overlap);
   
   //set higher priority for spi than hspi
   SET_PERI_REG_MASK(SPI_EXT3(SPI),0x1);
   SET_PERI_REG_MASK(SPI_EXT3(HSPI),0x3);
  SET_PERI_REG_MASK(SPI_USER(HSPI), BIT(5));

 //select HSPI CS2 ,disable HSPI CS0 and CS1
 CLEAR_PERI_REG_MASK(SPI_PIN(HSPI), SPI_CS2_DIS);
 SET_PERI_REG_MASK(SPI_PIN(HSPI), SPI_CS0_DIS |SPI_CS1_DIS);

 //SET IO MUX FOR GPIO0 , SELECT PIN FUNC AS SPI CS2
//IT WORK AS HSPI CS2 AFTER OVERLAP(THERE IS NO PIN OUT FOR NATIVE HSPI CS1/2)
 PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO0_U, FUNC_SPI_CS2);
}

In this demo , we drive a spi screen and share the data and clock lines with the spi flash.

Work with a gyroscope:

esp_iot_sdk_v0.9.2_hspi_overlap_141124.rar

Statistics: Posted by costaud — Mon Nov 24, 2014 2:06 am