ESP8266 Developer Zone The Official ESP8266 Forum 2015-04-27T02:44:14+08:00 https://bbs.espressif.com:443/feed.php?f=7&t=406 2015-04-27T02:44:14+08:00 2015-04-27T02:44:14+08:00 https://bbs.espressif.com:443/viewtopic.php?t=406&p=1521#p1521 <![CDATA[High priority interrupts]]>
I would like to know how to configure them to be able to have a High prio interrupt for SPI (or other peripheral) to avoid the rather long interrupt latency (>1uS ) induced by the "shared ISR" of the level 1 interrupt handler where the ESP_ISR_ATTACH() functions links interrupts related to SPI, GPIO....

Here is the same topic posted in the HDK section: http://bbs.espressif.com/viewtopic.php?f=6&t=405

Any hints greatly appreciated.

regards,
MCulibrk

Statistics: Posted by mculibrk — Mon Apr 27, 2015 2:44 am

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