ESP8266 Developer Zone

Re: ICACHE_FLASH_ATTR

2015-06-30T04:06:04+08:00

@Helios: thank you for your reply, but it doesn't answer any of my questions above

I know that the cache purpose is to automatically load instructions for the CPU, and that this operation is more or less transparent to the application program: not completely though, since you need these "ICACHE_FLASH_ATTR" decorations, and that program normal execution is probably suspended for a while during prefetch (how long?).

I would like to have more details on the "optimized replacing algorithm": is it page-based or function-based? What is the maximum (page or function) contiguous size? What happen in the case the missing part is larger than this maximum size?

Are there several simultaneous cache areas or just a single one? What do you mean by "optimized replacing algorithm": is it round-robbin, oldest, newest, least used (as I don't know of other ones)?

Is it better to write small functions or bigger ones?

Thank you for your help!

Statistics: Posted by Squonk — Tue Jun 30, 2015 4:06 am

Re: ICACHE_FLASH_ATTR

2015-06-23T20:05:12+08:00

The cache inside ESP8266 will automatically fill instructions for CPU, so its operations are transparent for Software. The cache does prefetch the data for CPU and apply the optimized replacing algorithm.
Software designer can apply the instruction space up to 1Mbytes. For the details, please refer to the ESP8266 "Programming Guide" and "User Manual".
In addition, some Read-only data can be in instruction space and can be accessed by C codes.

However, the interrupt handler shall not be in the cache space. The reason is that when programming some data into Flash, the cache must be disabled.

Statistics: Posted by Helios — Tue Jun 23, 2015 8:05 pm

ICACHE_FLASH_ATTR

2015-06-18T03:48:18+08:00

I know that according to the FAQ, the functions that are not decorated with the "ICACHE_FLASH_ATTR" macro are loaded into RAM at boot time, and that the functions decorated with " ICACHE_FLASH_ATTR" are loaded into RAM when required.

But can someone from Espressif explain in more details what is going on for the cache system? Here are the technical questions I cannot answer based on the current documentation or discussions in the BBS:

how is a "required" function detected? Is it a kind of page fault mechanism similar to more complex MMUs?
is this cache mechanism implemented in hardware or in software or a mix of both? If software, is it perform by ROM-based code?
are interrupts available while a function is loaded this way into RAM?
is it only the required function loaded into RAM, or is it a full memory "page" containing the function that is loaded into RAM?
if the system is using pages, how many pages can be loaded into RAM at any given time, and what size are these pages?
what addresses in memory are used for the cache?
in case there are more functions / pages loaded into RAM than physically available, what priority mechanism is used to choose the pages to replace, is it round-robbin, oldest, newest, least used?
if the cache system is using pages, what happen if a function with "ICACHE_FLASH_ATTR" decoration crosses a page boundary? Does it automatically trigger loading the next page into RAM?

I know these questions are very detailed, but answers to these would help all developers understand the "magic" (until now) cache mechanism and use the ESP8266 in a much more efficient way!

Statistics: Posted by Squonk — Thu Jun 18, 2015 3:48 am