hi
saw a problem in the HSPI in MODEN ( 0,1 ) and try to reproduce it now.
i experiment just in time with the HSPI and an extra GPIO-04 for SS ( /CS ).
for /cs on start there is no problem, for /cs after HSPI transaction is a problem
if the HSPI transfer is not finnished, the /cs can be done to early.
( left side of picture )
problem one: ( red arrow)
how we can check the register, that HSPI transaction is done, to set the /CS then back?
a delay cycle ( right side picture ) for the /cs back is not a option, because if the CLK speed is change to fast,
the delay is to short, and if CLK speed lower, the delay is to long.
problem two: ( yellow lines)
HSPI with Mode
CPOL: 0 ( clock is low if inactive )
CPHA: 1 ( data valid on trailing edge )
when MOSI last bit is send, the CLK is same time finnished same Time Mosi end the communication,
that is a problem, we get allways '0' for this moment on the clock trailing edge, never get the last bit correct.
FYI: Byte 0xFF was send, the last bit never would be read, so we have 0xFE on logicanalyzer
can we extend the last mosi bit or shorten the CLK on last bit by register flags?
thanks
best wishes
rudi
