ESP SPI slave mode and preventing the on-wire command bits

[cap]

Hello.

I have ESP SPI interface in slave mode working when connected to a non ESP SPI master. Prototyping/experimenting indicates the ESP SPI slave interface needs to receive at least command bits at the start of the SPI transaction. Without the command bits the ESP does not receive nor is able to send data on SPI.

Is my understanding correct? Is it possible to use the SPI slave interface of ESP without having to send the command bits? How if yes? The need is to use the ESP SPI in slave mode as a plain bit (or byte) stream, where the higher layers of the application will address the transfer direction.

Thanks to the author of http://d.av.id.au/blog/hardware-spi-hspi-command-data-registers/ and contributor/s to http://www.esp8266.com/viewtopic.php?f=13&t=2413, for the valuable analysis of the interface.

The ESP SDK example in “peripheral_test/user/spi_test,c" and "driver_lib/driver/spi*c" files are usable for reference. The relevant documentation I found is the "esp8266-technical_reference_en_0.pdf" sections 4.3 - 4.5, 6.3 and 6.4.444.

As an aside: it was possible to eliminate the address and status bits on the wire at the transaction start.

[pratik]

Hello,

You could individually control the various phases of the data transfer. Please consult the SPI register map for reference:
viewtopic.php?f=7&t=85

[cap]

Hello, Pratik.

Thanks for your response. From the ESP technical reference guide I can understand that when the ESP is in master mode these command bits can be eliminated. When in slave mode the user program does not receive any callbacks if the SPI master does not include the command bits. The ESP SPI slave does receive if the SPI master includes the other bits (correcting my first message). The register configuration that works, and the bytes sent by SPI master that actually work are below.

Could you be more specific please? An example code snippet will be even more helpful.


The setting that works, but needs the SPI master to send two extra bytes is below.

Code: Select all

        // By default format::CMD(4bits)+ADDR(4bits)+DATA(32bytes).
        SET_PERI_REG_BITS(SPI_USER2(spiNum), SPI_USR_COMMAND_BITLEN,
                          3, SPI_USR_COMMAND_BITLEN_S);
        SET_PERI_REG_BITS(SPI_SLAVE1(spiNum), SPI_SLV_WR_ADDR_BITLEN,
                          3, SPI_SLV_WR_ADDR_BITLEN_S);
        SET_PERI_REG_BITS(SPI_SLAVE1(spiNum), SPI_SLV_RD_ADDR_BITLEN,
                          3, SPI_SLV_RD_ADDR_BITLEN_S);
        SET_PERI_REG_BITS(SPI_SLAVE1(spiNum), SPI_SLV_BUF_BITLEN,
                          (32 * 8 - 1), SPI_SLV_BUF_BITLEN_S);
        // For 8266 work on slave mode.
        SET_PERI_REG_BITS(SPI_SLAVE1(spiNum), SPI_SLV_STATUS_BITLEN,
                          3, SPI_SLV_STATUS_BITLEN_S);

and on non ESP SPI master following is sent:

Code: Select all

     send_buffer[0] = 0x02;  // Bit 7:4 = 4 bit Address = 0; Bit 3:0 = 4 bit Command = 0x2 for send
     send_buffer[1] = 0x00;  // 8 bit dummy
     for(int i = 0; i < 32; i += 4) {
         *(unsigned int *)(&send_buffer[i + 2]) = test_pattern ++;
     }
     spi.send(send_buffer,34); // Send write command + data
     send_buffer[0] = 0x03;  // Bit 7:4 = 4 bit Address = 0; Bit 3:0 = 4 bit Command = 0x3 for receive
     send_buffer[1] = 0x00;  // 8 bit dummy
     spi.send(send_buffer, 2); // Send read  command
     spi.receive(buffer,32);

[cap]

Hello!

Requesting again: Can anyone provide example code/snippets that have been tested for ESP as SPI slave while not requiring command, status, and address bit information to be sent to it at the start of SPI transaction?

In the same context, is the ESP's SPI interface expected to function in full duplex when a SPI slave? It will help to know if it has been tried.

Please refer to my post/response to this for code snippets that I have used.