I would like to know how to configure them to be able to have a High prio interrupt for SPI (or other peripheral) to avoid the rather long interrupt latency (>1uS ) induced by the "shared ISR" of the level 1 interrupt handler where the ESP_ISR_ATTACH() functions links interrupts related to SPI, GPIO....
Here is the same topic posted in the HDK section: http://bbs.espressif.com/viewtopic.php?f=6&t=405
Any hints greatly appreciated.
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