Is there a limitation of 4-byte alignment only when crossing a boundary of the memory of the value 0x100?
Let me try to rephrase, If I write 6 bytes to the SPI flash from 0x71000 it will write to 0x71005 then the pointer will move to the next address 071006 to await more data... from this point if I kept writing lets say any length of data it will write all the way to 0x710fd just fine... now.. the pointer moves to 0x071fe and I write 4 bytes BOOM! SPI_FLASH_RESULT_ERR! .... now I was thinking, may it's just that address.. I erased and updated my code to point to 0x07000 and it starts cranking and then it lands right on 0x700fe as predicted and BOOM, the Same issue... Does anyone have any technical background on this? Like is the SPI flash like physically segmented at the 0x100 block interval or is it something else?
See the thing is I feel the problem is that a length is exactly a number that lands inside the four-byte alignment of the next block.
In this case, if I would have written the data it would have written 4 bytes into 0x700fe, 0x700ff, 0x70100, 0x70101 and I think that's were the issue is...
Code: Select all
os_printf("stackptr is %x remainder is %u", SPIStackWritePtr, (SPIStackWritePtr % 0x100));
if (SPIStackWritePtr % 0x100 < 4 )
os_printf("stackptr is %x setting to +%u\r\n", SPIStackWritePtr, (SPIStackWritePtr % 0x100));
SPIStackWritePtr += (SPIStackWritePtr % 0x100);
os_printf("stackptr is now %x\r\n", SPIStackWritePtr);
stackptr is 710fe remainder is 2stackptr is 710fe setting to +2
stackptr is now 71100
Writing SPI Data BinaryVoidLen:6 - 106 to 0x71100...
Written BinaryVoidLen:6 to 0x71100 SPI Data written...
Writing SPI Data BinaryVoidData from 0x71104 to 0x71109...
Written BinaryVoidData from 0x71104 to 0x71109...
0x51 0x01 0xC3 0xAF 0x8E 0x5C
https://www.espressif.com/sites/default ... nce_en.pdf
Along with debug testing it seems I can pretty much write anywhere I want with any length of bytes as long as its less then or equal to 256 bytes AND my writes do not cross the borders with a modulus of 0x100 (Dec 256). I think the PDF needs to be updated to reflect this instead of the "4 byte alignment" as described in the document is incorrect?
My notes on this are below, I will craft my logging logic based on these restrictions...
3/18/19 - SPI flash Rules
There are 4096 sets of Pages, Each page contains 256 Bytes
Each Sector holds 16 pages and can be erased at once
You may write only up to 256 Bytes Max per a single write
You may not write across boundary address 0x???FF to 0x??100
Entering into a different page in a single write will cause an SPI error
BEWEAR! Reading less than 4 bytes will keep the old bytes from the previous read in the return buffer
Pages can be erased in groups of 16 (4KB sector erase), Groups of 128, groups of 256 or the entire chip.
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