I'd like to know what is the XPD_DCDC state while the ESP8285 is in deep sleep.
Is it at high logic level?
Or is it at high impedance?
In other words: Is it an open drain GPIO during deep sleep?
You can refer to the ESP8266 Pin List: http://www.espressif.com/en/support/download/documents.
It is at high logic level.
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