The following questions come to mind:
a. The VDDPST explicitly does not need a decoupling capacitor. Does that mean that it merely pulls a completely flat DC current? I'd normally say that a decoupling capacitor there is still desirable, but the size depends on the kind of frequency. I'm guessing, but internally the chip seems to be clocked at 80MHz, so I'd normally dimension a decoupling capacitor for that frequency.
b. In some design guides I see a 10uF close to VDD3P3 and a 0.1uF close to VDDA and VDDD. In other guides I see a 10uF and a 0.1F close to VDD3P3 and a 10uF on VDDA and VDDD. And in some guides the last 10uF on VDDA and VDDD is replaced by a 1uF capacitor.
Can someone explain the different design considerations there?
c. What's the difference between VDD3P3, VDDA and VDDD ?Statistics: Posted by BuGless — Wed Sep 09, 2015 2:50 am
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