ESP8266 Developer Zone

Re: ADC for 50 Hz signal

2016-07-20T18:14:03+08:00

Followup on ADC sampling rate:
- Minimum ADC clock divisor is 8. Therefore, max frequency is 10MHz.
- It takes about 20 cycles to perform a conversion.
- When using fast_read API, assume a conversion time of about 5 us.

Statistics: Posted by Guest — Wed Jul 20, 2016 6:14 pm

Re: ADC for 50 Hz signal

2016-07-17T22:43:17+08:00

Hello Zaved,

The ADC should be able to sample at 500Hz without problems. You may use timer interrupts to sample the analog input at a constant frequency.
However, writing to flash will need a write buffer implementation because the APIs write 4kB at a time and write operation may take an unknown amount of time depending on what chip you are using and DIO/QIO, clock speed, etc.
Also, modem sleep is recommended when you are running sampling applications. Otherwise network stack tasks will disturb your sampling process in between at times.

Statistics: Posted by Guest — Sun Jul 17, 2016 10:43 pm

[SOLVED] ADC for 50 Hz signal

2016-07-17T13:14:03+08:00

Hi all
Is it possible to perform ADC on a 50 Hz signal around 512 points of samples( sampling frequency 500Hz). Please let me know if there is a API for this. Also , if I can use system_adc_read_fast() for this. How many clock cycle it requires to have one ADC performed and store it in the flash? Where can I find these information?

Thanks
Zaved

Statistics: Posted by zaved — Sun Jul 17, 2016 1:14 pm