ESP8266 Developer Zone The Official ESP8266 Forum 2020-05-01T18:27:25+08:00 https://bbs.espressif.com:443/feed.php?f=66&t=56814 2020-05-01T18:27:25+08:00 2020-05-01T18:27:25+08:00 https://bbs.espressif.com:443/viewtopic.php?t=56814&p=77691#p77691 <![CDATA[Re: Hardware bug: UART1 TX level not mirrored in status register]]> Statistics: Posted by RFZ — Fri May 01, 2020 6:27 pm

]]> 2020-04-19T01:58:16+08:00 2020-04-19T01:58:16+08:00 https://bbs.espressif.com:443/viewtopic.php?t=56814&p=76742#p76742 <![CDATA[Hardware bug: UART1 TX level not mirrored in status register]]> I guess I may have found a bug in the ESP8266 hardware / UART1 interface. Bit 31 of register 0x60000F1C (UART1 status register) should mirror the TX level of UART1. However, I found it to be always 0.

A workaround is actually to enable loopback mode for UART1 and read bit 15 of register 0x60000F1C, which mirrors the RX level. Since UART1 is TX only (?) that's not a huge problem.

The code I used to test this can be found here:
https://www.esp8266.com/viewtopic.php?f=13&t=21169&start=12

I'd appreciate if someone can confirm this.

Statistics: Posted by RFZ — Sun Apr 19, 2020 1:58 am

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