ESP8266 Developer Zone

Re: "section .text will not fit into region iram1_0 seg" ?

2018-08-03T00:11:26+08:00

Wow, your solution is working for me. Thank you Pratik.
I've been struggling with this issue for a few hours until I found your post. Now I can sleep with smile.

Statistics: Posted by simonliu — Fri Aug 03, 2018 12:11 am

Re: "section .text will not fit into region iram1_0 seg" ?

2017-01-20T13:28:25+08:00

Code:

  .irom0.text : ALIGN(4)
  {
    _irom0_text_start = ABSOLUTE(.);
    
    *libpwm.a:(.literal .text .literal.* .text.*)
    
    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)
    _irom0_text_end = ABSOLUTE(.);
  } >irom0_0_seg :irom0_0_phdr

Something like this. If you are not sure which LD file is being used in your compile settings, modify all LD files, this modification may not work for all libraries, so see if this works for you!

Statistics: Posted by Guest — Fri Jan 20, 2017 1:28 pm

Re: "section .text will not fit into region iram1_0 seg" ?

2017-01-18T17:56:15+08:00

Here is my ld file (eagle.app.v6.ld):

Code:

/* This linker script generated from xt-genldscripts.tpp for LSP . */
/* Linker Script for ld -N */
MEMORY
{
  dport0_0_seg :                        org = 0x3FF00000, len = 0x10
  dram0_0_seg :                         org = 0x3FFE8000, len = 0x14000
  iram1_0_seg :                         org = 0x40100000, len = 0x8000
  irom0_0_seg :                         org = 0x40240000, len = 0x3C000
}

PHDRS
{
  dport0_0_phdr PT_LOAD;
  dram0_0_phdr PT_LOAD;
  dram0_0_bss_phdr PT_LOAD;
  iram1_0_phdr PT_LOAD;
  irom0_0_phdr PT_LOAD;
}


/*  Default entry point:  */
ENTRY(call_user_start)
EXTERN(_DebugExceptionVector)
EXTERN(_DoubleExceptionVector)
EXTERN(_KernelExceptionVector)
EXTERN(_NMIExceptionVector)
EXTERN(_UserExceptionVector)
PROVIDE(_memmap_vecbase_reset = 0x40000000);
/* Various memory-map dependent cache attribute settings: */
_memmap_cacheattr_wb_base = 0x00000110;
_memmap_cacheattr_wt_base = 0x00000110;
_memmap_cacheattr_bp_base = 0x00000220;
_memmap_cacheattr_unused_mask = 0xFFFFF00F;
_memmap_cacheattr_wb_trapnull = 0x2222211F;
_memmap_cacheattr_wba_trapnull = 0x2222211F;
_memmap_cacheattr_wbna_trapnull = 0x2222211F;
_memmap_cacheattr_wt_trapnull = 0x2222211F;
_memmap_cacheattr_bp_trapnull = 0x2222222F;
_memmap_cacheattr_wb_strict = 0xFFFFF11F;
_memmap_cacheattr_wt_strict = 0xFFFFF11F;
_memmap_cacheattr_bp_strict = 0xFFFFF22F;
_memmap_cacheattr_wb_allvalid = 0x22222112;
_memmap_cacheattr_wt_allvalid = 0x22222112;
_memmap_cacheattr_bp_allvalid = 0x22222222;
PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);

SECTIONS
{

  .dport0.rodata : ALIGN(4)
  {
    _dport0_rodata_start = ABSOLUTE(.);
    *(.dport0.rodata)
    *(.dport.rodata)
    _dport0_rodata_end = ABSOLUTE(.);
  } >dport0_0_seg :dport0_0_phdr

  .dport0.literal : ALIGN(4)
  {
    _dport0_literal_start = ABSOLUTE(.);
    *(.dport0.literal)
    *(.dport.literal)
    _dport0_literal_end = ABSOLUTE(.);
  } >dport0_0_seg :dport0_0_phdr

  .dport0.data : ALIGN(4)
  {
    _dport0_data_start = ABSOLUTE(.);
    *(.dport0.data)
    *(.dport.data)
    _dport0_data_end = ABSOLUTE(.);
  } >dport0_0_seg :dport0_0_phdr

  .data : ALIGN(4)
  {
    _data_start = ABSOLUTE(.);
    *(.data)
    *(.data.*)
    *(.gnu.linkonce.d.*)
    *(.data1)
    *(.sdata)
    *(.sdata.*)
    *(.gnu.linkonce.s.*)
    *(.sdata2)
    *(.sdata2.*)
    *(.gnu.linkonce.s2.*)
    *(.jcr)
    _data_end = ABSOLUTE(.);
  } >dram0_0_seg :dram0_0_phdr

  .rodata : ALIGN(4)
  {
    _rodata_start = ABSOLUTE(.);
    *(.sdk.version)
    *(.rodata)
    *(.rodata.*)
    *(.gnu.linkonce.r.*)
    *(.rodata1)
    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
    *(.xt_except_table)
    *(.gcc_except_table)
    *(.gnu.linkonce.e.*)
    *(.gnu.version_r)
    *(.eh_frame)
    /*  C++ constructor and destructor tables, properly ordered:  */
    KEEP (*crtbegin.o(.ctors))
    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
    KEEP (*(SORT(.ctors.*)))
    KEEP (*(.ctors))
    KEEP (*crtbegin.o(.dtors))
    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
    KEEP (*(SORT(.dtors.*)))
    KEEP (*(.dtors))
    /*  C++ exception handlers table:  */
    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
    *(.xt_except_desc)
    *(.gnu.linkonce.h.*)
    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
    *(.xt_except_desc_end)
    *(.dynamic)
    *(.gnu.version_d)
    . = ALIGN(4);      /* this table MUST be 4-byte aligned */
    _bss_table_start = ABSOLUTE(.);
    LONG(_bss_start)
    LONG(_bss_end)
    _bss_table_end = ABSOLUTE(.);
    _rodata_end = ABSOLUTE(.);
  } >dram0_0_seg :dram0_0_phdr

  .bss ALIGN(8) (NOLOAD) : ALIGN(4)
  {
    . = ALIGN (8);
    _bss_start = ABSOLUTE(.);
    *(.dynsbss)
    *(.sbss)
    *(.sbss.*)
    *(.gnu.linkonce.sb.*)
    *(.scommon)
    *(.sbss2)
    *(.sbss2.*)
    *(.gnu.linkonce.sb2.*)
    *(.dynbss)
    *(.bss)
    *(.bss.*)
    *(.gnu.linkonce.b.*)
    *(COMMON)
    . = ALIGN (8);
    _bss_end = ABSOLUTE(.);
    _heap_start = ABSOLUTE(.);
/*    _stack_sentry = ALIGN(0x8); */
  } >dram0_0_seg :dram0_0_bss_phdr
/* __stack = 0x3ffc8000; */

  .text : ALIGN(4)
  {
    _stext = .;
    _text_start = ABSOLUTE(.);
    *(.UserEnter.text)
    . = ALIGN(16);
    *(.DebugExceptionVector.text)
    . = ALIGN(16);
    *(.NMIExceptionVector.text)
    . = ALIGN(16);
    *(.KernelExceptionVector.text)
    LONG(0)
    LONG(0)
    LONG(0)
    LONG(0)
    . = ALIGN(16);
    *(.UserExceptionVector.text)
    LONG(0)
    LONG(0)
    LONG(0)
    LONG(0)
    . = ALIGN(16);
    *(.DoubleExceptionVector.text)
    LONG(0)
    LONG(0)
    LONG(0)
    LONG(0)
    . = ALIGN (16);
    *(.entry.text)
    *(.init.literal)
    *(.init)
    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
    *(.fini.literal)
    *(.fini)
    *(.gnu.version)
    _text_end = ABSOLUTE(.);
    _etext = .;
  } >iram1_0_seg :iram1_0_phdr

  .lit4 : ALIGN(4)
  {
    _lit4_start = ABSOLUTE(.);
    *(*.lit4)
    *(.lit4.*)
    *(.gnu.linkonce.lit4.*)
    _lit4_end = ABSOLUTE(.);
  } >iram1_0_seg :iram1_0_phdr

  .irom0.text : ALIGN(4)
  {
    _irom0_text_start = ABSOLUTE(.);
    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)
    _irom0_text_end = ABSOLUTE(.);
  } >irom0_0_seg :irom0_0_phdr
}

/* get ROM code address */
INCLUDE "eagle.rom.addr.v6.ld"

Could you please point me where the line you mentioned

Code:

*libpwm.a:(.literal .text .literal.* .text.*)

should be placed within the text above in order to move the library to flash memory. Does it work in the same way for other libraries?

Thanks!

Statistics: Posted by russus — Wed Jan 18, 2017 5:56 pm

Re: "section .text will not fit into region iram1_0 seg" ?

2016-11-12T12:27:00+08:00

You may actually try to relocate the PWM library to flash by modifying the LD files. I'm sure it will compile then, but not sure if the PWM functions will work reliably (did not test it out yet). You may try this if you want to:

In the ld folder of nonOS SDK v.2.0.0, open all ld files and find this line:
*libmbedtls.a:(.literal .text .literal.* .text.*)

Add this line below it:
*libpwm.a:(.literal .text .literal.* .text.*)

This will specify that the pwm library should be placed in the iCache. Let me know if this causes crashes (internal SDK code is not known to me). If this fails, I will request a firmware developer to assist you.

Statistics: Posted by Guest — Sat Nov 12, 2016 12:27 pm

Re: "section .text will not fit into region iram1_0 seg" ?

2016-10-10T21:35:46+08:00

Data doesn't go into IRAM, it goes to DRAM (or remains in flash if you explicitly keep it there).

Biggest hog of IRAM space still is the SDK code, unfortunately.

Statistics: Posted by eriksl — Mon Oct 10, 2016 9:35 pm

"section .text will not fit into region iram1_0 seg" ?

2016-09-19T23:52:48+08:00

Hi all,

When we compile the SDK 2.0.0 with AT support additionally with some our customised AT commands, we encountered a problem saying that
output/eagle/debug/image/eagle.app.v6.out section section .text will not fit into region iram1_0 seg.
collect2: error: ld return 1 exit status
Kindly noticed that, it is not a problem that not fit into region "irom0_0_seg", but "iram1_0 seg".

A space of total max 32KB(0x8000) bytes from 0x4010 0000 is used as iRam by bootload to load code from spi flash. Therefore it seem that we CAN NOT increase the size here since it is already defined as max 0x8000 bytes in the ld file as such for iRom segs.

Meanwhile, we add ICACHE_FLASH_ATTR to all the functions we customised, but it does not make much difference. The only way we find so far is to remove the cutomised AT functions. However, this issue is not present with SDK 1.4.0 etc.

Any suggestions here? Sure, we don't expect to remove some of our customised AT functions for previous conpatibility.

Thanks,

Yiming Li

Statistics: Posted by Guest — Mon Sep 19, 2016 11:52 pm