UART cause esp8266 reboot

[wjzhang]

Hi, when i try send esp8266 uart as much as possible datas, it caused the reboot.
it show " ets Jan 8 2013,rst cause:2, boot mode:(6,6) \r\n waiting for host" (foget the boot mode first 6)

the UART is set enable RTS/CTS. and the RTS also rise and fall. the test client stop send data when esp8266 rise the RTS signal. it restart send when esp8266 RTS fall.

//set Rx hardware flow control
if((pconfig->hwflowctrl == USART_HardwareFlowControl_CTS_RTS) || (pconfig->hwflowctrl == USART_HardwareFlowControl_RTS))
{
SET_PERI_REG_MASK(UART_CONF1(uart_no), ((0x78 & UART_RX_FLOW_THRHD) << UART_RX_FLOW_THRHD_S) | UART_RX_FLOW_EN );
}

in the UART ISR, read data from FIFO, stored to buffer(512 bytes size), then system_os_post() to active the UART task to handle these datas. the UART task queue size is 64. (512/(128*3/4)= 5.333)

[costaud]

Hi, when i try send esp8266 uart as much as possible datas, it caused the reboot.
it show " ets Jan 8 2013,rst cause:2, boot mode:(6,6) \r\n waiting for host" (foget the boot mode first 6)

the UART is set enable RTS/CTS. and the RTS also rise and fall. the test client stop send data when esp8266 rise the RTS signal. it restart send when esp8266 RTS fall.

//set Rx hardware flow control
if((pconfig->hwflowctrl == USART_HardwareFlowControl_CTS_RTS) || (pconfig->hwflowctrl == USART_HardwareFlowControl_RTS))
{
SET_PERI_REG_MASK(UART_CONF1(uart_no), ((0x78 & UART_RX_FLOW_THRHD) << UART_RX_FLOW_THRHD_S) | UART_RX_FLOW_EN );
}

in the UART ISR, read data from FIFO, stored to buffer(512 bytes size), then system_os_post() to active the UART task to handle these datas. the UART task queue size is 64. (512/(128*3/4)= 5.333)

Hello,
would you please send your test code to feedback@espressif.com? We will try to figure out what the problem is ASAP.

[wjzhang]

Hi,
if the FIFO still has data, could WRITE_PERI_REG(UART_INT_CLR(UART0), UART_RXFIFO_FULL_INT_CLR) and WRITE_PERI_REG(UART_INT_CLR(UART0), UART_RXFIFO_TOUT_INT_CLR) clear the interrupt? also include the Overrun interrupt?

[wjzhang]

Sorry, forget another question, if system_os_post() send more than task event queue max size, what's happened?
for example, our UART task has max 64 events, but UART ISR may has more 64 interrupts when UART task process first event.

[wjzhang]

hi, it seem the failed to clear interrupt by WRITE_PERI_REG(UART_INT_CLR(UART0), UART_RXFIFO_FULL_INT_CLR) / WRITE_PERI_REG(UART_INT_CLR(UART0), UART_RXFIFO_TOUT_INT_CLR) when FIFO still has data. the UART always rise interrupt and cause esp8266 reboot. but why the reset cause show 2 ?

void uart0_disable_interrupt(void)
{
//disable rx interrupt
CLEAR_PERI_REG_MASK(UART_INT_ENA(UART0), UART_RXFIFO_FULL_INT_ENA|UART_RXFIFO_TOUT_INT_ENA | UART_RXFIFO_OVF_INT_ENA | UART_FRM_ERR_INT_ENA | UART_PARITY_ERR_INT_ENA);
}
void uart0_enable_interrupt(void)
{
//enable rx interrupt
SET_PERI_REG_MASK(UART_INT_ENA(UART0), UART_RXFIFO_FULL_INT_ENA|UART_RXFIFO_TOUT_INT_ENA | UART_RXFIFO_OVF_INT_ENA | UART_FRM_ERR_INT_ENA | UART_PARITY_ERR_INT_ENA);
}
when read all FIFO datas, call WRITE_PERI_REG() clear interrupt, disable uart0 interrupt when Receive buffer is full, and in task re-enable uart0 interrupt when Receive buffer is empty, it never reboot.