[SOLVED] Possible to setup UART with no stop bit?

[sporadic]

I'm using the UART to generate a custom data stream and am curious if there is a way to have it not generate a stop bit? I attempted to configure it as 8N0, but it is behaving as 8N1 and generating a stop bit. Is there way to do this?

[pratik]

Hello,

That is strange! I have never heard of a no-stop-bit UART. There is no hardware support for that, sorry. As far as I know, most chips won't have hardware support for that.
You could do that with simple software GPIO (bit-banging) as UART is pretty slow anyway. The ESP8266 can deliver 300kbps easily with bit banging.
But I would not recommend doing this unless it is an absolute necessity. The stream will be misaligned and be full of errors very easily.

[sporadic]

Hello,

That is strange! I have never heard of a no-stop-bit UART. There is no hardware support for that, sorry. As far as I know, most chips won't have hardware support for that.
You could do that with simple software GPIO (bit-banging) as UART is pretty slow anyway. The ESP8266 can deliver 300kbps easily with bit banging.
But I would not recommend doing this unless it is an absolute necessity. The stream will be misaligned and be full of errors very easily.

I have a bit-bang implementation in place, however the packet takes too long to generate with interrupts disabled (790us) and I get watchdog resets. Is there any way to get around this? The characteristics of the expected signal are as follows:

Code: Select all

idle (>30us low)
start (10us hi)
26 bits (30us each)

0 = 10us low / 20us high
1 = 20us low / 10us high


I also have an implementation using 7N1 with a lookup table that shifts and generates the appropriate bits based off a 300kHz bit rate, generating 1 byte on the UART per bit of data. It utilizes the start and stop bits as part of the stream:

Code: Select all

const char LOOKUP_GECE[2] = {
    0b01111100,     // 0 - (0)00 111 11(1) <- signal on line
    0b01100000      // 1 - (0)00 000 11(1) <- signal on line
};


However, I can't run inverted due to start/stop bit alignment and need to immediately set a break to pull the line low after the bytes have been sent. I have a non-interrupt driven solution that seems to work, but I would like to offload this to an interrupt handler. With that, I have one more question What is the expected behavior of setting UART_TDX_BRK if there is data in the FIFO? From what I've seen, the break is set immediately after the FIFO has been emptied. Is this the intended behavior? If so, I may have a solution to my problem. Thanks!

[pratik]

Hello,

I have attached 2 documents from past Espressif documentation releases that can provide you with the details regarding UART behavior. The behavior is pretty much the same as any standard UART peripheral.
But for your specific case, I would still recommend bit-banging the interface.
For offloading the processor, you may use hw_timer APIs and see if they serve the purpose.
For preventing watchdog timer problems, go with wdt_feed or wdt_stop APIs.
Please consult the API documentation of whichever SDK you are using.

If you want to debug the hardware in detail, I would recommend using a scope to see the signal timings. The Wi-Fi circuitry of the ESP8266 may disrupt things if you do not configure timer interrupts properly.