XPD_DCDC state while in deep sleep

[hatus]

Hi,

I'd like to know what is the XPD_DCDC state while the ESP8285 is in deep sleep.

Is it at high logic level?

Or is it at high impedance?

In other words: Is it an open drain GPIO during deep sleep?

Thank you.

Best regards,
Hatus

[ESP_Faye]

Hi,

You can refer to the ESP8266 Pin List: http://www.espressif.com/en/support/download/documents.
It is at high logic level.

Thanks for your interest in ESP8266 !